The STARTUPE3 design element is used to connect to selected dedicated configuration pins (located in bank 0). Control of dedicated configuration pins allows post-configuration access to the flash. When the flash is only used for configuration the FPGA design does not require the STARTUPE3.
For multi-purpose configuration pins located
in bank 65, standard user logic can be implemented to connect to the pins required for access
to the flash, with appropriate location constraints. For example, when using x8 or wider
configuration modes, the STARTUPE3 is only used for the four LSBs of the configuration bus,
D[03:00] located within bank 0. The higher order pins
D[xx:04] can be directly connected as part of the user design.
The STARTUPE3 primitive for the UltraScale architecture-based FPGAs does not provide specification
of the startup clock as was done in the STARTUPE2 for the 7 series. Otherwise, STARTUPE3 is a superset of STARTUPE2, and designs
are retargeted automatically. The STARTUPE3 adds the ability to control the
D00-D03 pins and the FCS_B pin as these pins are now in
the dedicated configuration bank. The bidirectional D00-D03 pins have
separate input and output connections to the STARTUPE3. Additional configuration pins can be
controlled after configuration as standard I/O, including bidirectional I/O.
For devices based on Stacked Silicon Interconnect (SSI) technology, a single STARTUPE3 in the design is implemented in the master SLR and is automatically replicated to the other SLRs to provide global control of the device.