Serial NOR flash devices clock data out on the falling edge and by default, the UltraScale FPGAs clock data in on the rising edge. This results in a lost half cycle that limits the maximum clock speed of the configuration solution (see the following figure). To gain maximum use of the clock period, the FPGA can be configured to clock data in on the falling edge.
When configuration starts, the FPGA clocks data in on the rising edge. This continues until the FPGA reads the command in the early part of the bitstream that instructs it to change to the falling edge. This occurs before the command to change to external clocking or the command to change the master clock frequency. The falling edge clocking option is enabled in the Vivado tool Edit Device Properties dialog box (BITSTREAM.CONFIG.SPI_FALL_EDGE Yes).