SEU Detection and Correction - SEU Detection and Correction - UG570

UltraScale architecture-based FPGAs include the ability to do continuous readback of configuration data in the background of a user design. A cyclic redundancy code (CRC) check value from the readback data can be compared to a golden value to validate the integrity of the bitstream. This feature is aimed at simplifying detection of single event upsets (SEU) that cause a configuration memory bit to flip, and is used by the Soft Error Mitigation (SEM) IP.

After readback CRC is enabled, the dedicated configuration logic reads back continuously in the background to check the CRC of the configuration memory content. As some configuration bits can change during operation, such as distributed RAM, the readback CRC function masks these bits so that variable locations are ignored. These dynamically changeable memory locations are masked during background readback:

• SLICEM LUT (RAM or SRL).
• Block RAM content is skipped during readback to avoid interfering with user functions. Block RAM is optionally covered by its own ECC circuit during operation.
• Dynamic reconfiguration port (DRP) memories are masked.

When enabled, the readback CRC logic automatically runs in the background after configuration is DONE, and when these conditions hold:

• The FPGA is configured successfully, as indicated by the DONE pin going High.
• The configuration interface has been parked correctly. A normal bitstream has a DESYNC command at the end that signals to the configuration interface that it is no longer being used. The DESYNC command clears the CRC_ERROR flag.
• The JTAG interface is not controlling the internal configuration bus via the JTAG CFG_IN instruction, CFG_OUT instruction, or ISC_ENABLE function.

The SEM IP uses the ICAPE3 and runs the readback CRC on the ICAPE3 CLK source.

In UltraScale devices, any use of configuration readback (Readback CRC, SEM-IP, internal or external SEU scrubbing, and other configuration readback activities) or partial reconfiguration exercises data lines that have a small amount of coupling into the VCO of the MMCM and PLLs. As a result, varying amounts of increased time interval error jitter can be observed. See answer record 71314 for guidance and mitigation techniques. See the Vivado Design Suite User Guide: Programming and Debugging (UG908) for write_bitstream properties information.

In a partial reconfiguration application, the configuration memory content changes, so the golden signature must be recalculated. The golden CRC must be re-calculated by the SEM IP after any partial reconfiguration event. See Demonstration of Soft Error Mitigation IP and Partial Reconfiguration Capability on Monolithic Devices (XAPP1261).

The readback CRC will be interrupted by a reconfiguration command. Except when reconfiguring through JTAG, the readback CRC logic might need up to 130 clock cycles to complete before new configuration packets can be applied. Therefore, bitstreams that might be used to reconfigure a device running readback CRC should pad 130 NOOPs after the SYNC word.

For more information, see the SEM product page.