Revision History - Revision History

The following table shows the revision history for this document.

Section	Revision Summary
03/04/2025 Version 1.20.1
General updates	Editorial updates only. No technical content updates.
02/25/2025 Version 1.20
Overview	Updated to add references for Spartan UltraScale+ and Zynq UltraScale+ devices.
Power-On Reset	Changed TPOR delay end with the FPGA deasserting the INIT_B pin.
Continuous SelectMAP Data Loading	Updated to address CCLK requirement in SelectMAP.
Applications	Clarification update to add quotes to `.DISABLE_JTAG("TRUE")`.
References	Updated to add additional references.
6/12/2024 Version 1.19
General updates	Clarified Bitstream Encryption and Authentication and RSA Authentication. Updated Status Register (00111). Modified “Accessing Configuration Registers through the SelectMAP Interface” section to Accessing Configuration and Configuration Memory through the SelectMAP Interface to include accessing configuration memory.
11/17/2023 Version 1.18
General updates	Updated data for AU7P device in Table 1. Added last paragraph under Determining the Maximum Configuration Clock Frequency. Corrected Figure formatting in Bit Swapping. Clarified BSPI_READ description in Command Register (00100). Clarified last paragraph under Introduction and deleted ''Readback Capture'' section.
04/20/2023 Version 1.17
General updates	Added AMD Artix™ AU7P device and updated configuration bit stream length and configuration overhead values for KU085, KU115, vu125, VU160, VU190, and VU440 devices in Table 1. Added Artix AU7P device and second note in Table 2. Clarified first paragraph under POR_OVERRIDE. Changed voltages for pin D[31:00] in SPI mode from V_{CCO_65} to V_{CCO_0} in Configuration Pins. Clarified description for PROGRAM_B in Configuration Pins and step 5 in Accessing Configuration and Configuration Memory through the SelectMAP Interface. Updated figure in Master SPI Interface Added last paragraph to Introduction. Clarified descriptions in JTAG Instructions. Clarified Persist Option and added table.
01/14/2022 Version 1.16
General updates	Clarified RSA Authentication. Updated figure in Device Power-Up (Step 1).
09/09/2021 Version 1.15
General updates	Added coverage of Artix UltraScale+ AU10P, AU15P, AU20P, and AU25P devices: Added these devices to Table 1 and Table 2.
06/25/2021 Version 1.14
General updates	Added reference to UltraScale+ Devices Integrated Block for PCI Express Product Guide (PG213). Updated KU19P device data in Table 1. Added KU19P, VU23P, and VU57P production IDCODE revisions to Table 2. Clarified USR_ACCESSE2 Advanced Uses. Clarified Loading Encrypted Bitstreams. Added register bits [31:26] to Frame Address Register (00001) and URAM register code to Command Register (00100).
07/28/2020 Version 1.13
General updates	Added VU57P device to Differences in 3D ICs. Added KU19P, VU23P, and VU57P devices to Table 1 and Table 2. Updated JTAG Instructions descriptions for R_DIS_USER, R_DIS_SEC, and R_DIS_RSA. Updated Table Bitstream Composition description for configuration word 30026001. Added information for encrypted bitstreams using an obfuscated key with the JTAG, SelectMAP, or ICAP interfaces.
03/31/2020 Version 1.12
General updates	Added VU19P production IDCODE revision to Table 1. Updated value for GLUTMASK_B in Control Register 0 (00101).
09/30/2019 Version 1.11
General updates	Added coverage of Virtex UltraScale+ VU19P, VU47P, and VU49P devices. Updated production IDCODE revisions for Virtex UltraScale+ FPGAs in Table 1. Updated descriptions for INIT_B and DONE in Configuration Pins. Updated figures in Setup (Steps 1-3) and Start-up Sequence (Step 8). Added information to SEU Detection and Correction.
02/21/2019 Version 1.10
General updates	Added coverage of Virtex UltraScale+ VU27P and VU29P devices. Clarified description of DONE pin in Configuration Pins. Added section FRAME_ECCE4. Clarified Loading the Encryption Key. Clarified description of R_DIS_KEY in JTAG Instructions. Changed “24” to “64” in Clocking to End of Start-up. Clarified first paragraph under Serial Daisy Chain Configuration.
04/09/2018 Version 1.9
General updates	Added VU35P and VU37P devices to Differences in 3D ICs. Added VU31P, VU33P, VU35P, and VU37P devices to Table 1 and Table 2. Changed VREF to VCCO_0 in figures in Master SPI Quad (x4). Clarified Persist Option.
12/21/2017 Version 1.8
General updates	Clarified AES-CBC terminology throughout document. Updated Table 2. Added information to note 6 under tables in Configuration Pins. Clarified the minimum recommended operating voltage in second paragraph under Configuration Banks Voltage Select (Kintex UltraScale and Virtex UltraScale FPGAs) in Introduction. Updated External Master Configuration Clock (EMCCLK) Option in Introduction. Clarified bitstream generation under Master SPI Dual Quad (x8) inMaster SPI Configuration Mode. Added note under Master BPI Synchronous Read in Master BPI Configuration Mode. Clarified ABORT sequence support under RDWR_B in SelectMAP Configuration Modes. Added SelectMAP ABORT in SelectMAP Configuration Modes. Added last paragraph under Applications in Design Entry. Added UltraScale+ FPGAs column to RSA Authentication. Updated OTP eFUSE Registers. Added last paragraph under Device Power-Up (Step 1) and second paragraph under CRC Check (Step 7) in Configuration Details. Updated descriptions of RBCRC_ACTION in Table 9-30 and TIMER_CFG_MON in Watchdog Timer Register (10001). Clarified first paragraph and step 10 under Configuration Memory Read Procedure (SelectMAP) Readback Verification and CRC.
03/15/2017 Version 1.7
General updates	Clarified differences between UltraScale and UltraScale+ device families throughout document. Added UltraScale+ devices to Differences in 3D ICs. Added UltraScale+ device bitstream lengths to Table 1 and JTAG and IDCODEs Table 2. Added important note to Recommended Design Flow and Configuration Factors in Introduction. Removed input arrow heads from figures in SPI Flash DQ2 and DQ3 in Master SPI Configuration Mode. Added Additional Information in Master SPI Configuration Mode. Changed VCCO_0 to VCCO_65 in Slave Serial Configuration. Deleted reference to specific Parallel NOR flash device in Master BPI Synchronous Read. Change “byte-swapped” to “bit-swapped” under File Generation. Replaced fourth paragraph under Introduction. Clarified description of MASTER_JTAG in Design Entry. Added last paragraph under Bitstream Encryption and Authentication and last paragraph under Loading the Encryption Key. Clarified second paragraph under eFUSE. Corrected “0:255” to “255:0” in second row of OTP eFUSE Registers. Updated bit positions 6 and 7 in .Table 3. Updated format of the FPGA JTAG IDCODE register under Device ID Check (Step 5) in Configuration Details. Changed “03651093” to “03822093” in Bitstream Composition. Updated Configuration Options Register 0 (01001). Added last sentence under first paragraph under Configuration Memory Read Procedure (JTAG). Updated values in step 8 and step 10 of Configuration Register Read Procedure (JTAG). Changed “Readback CRC” to SEU Detection and Correction in Readback Verification and CRC. Added references to PG172, XAPP1191, XAPP1280, XAPP1267, XAPP1261, and XAPP1257 throughout document and in Additional Resources and Legal Notices.
12/16/2015 Version 1.6
General updates	Updated Table 1 and Table 2. Added last sentence to first paragraph under MASTER_JTAG in Design Entry. Added second paragraph and table under RSA Authentication to define restrictions as noted in XCN15038. Added last sentence to first paragraph under OTP eFUSE Registers. Added second sentence to paragraph in JTAG Instructions.
11/24/2015 Version 1.5
General updates	Added UltraScale+ device information. Added data to Table 2. Updated description of PROGRAM_B PUDC_B in Configuration Pin Definitions. Clarified text in Configuration Sequence. Clarified text in Device Power-Up (Step 1). Added PROGRAM_B to Table 1. Clarified second paragraph under Fallback MultiBoot.
09/15/2015 Version 1.4
General updates	Added configuration information for the KU025 device. Changed “SPI flash” to “Serial NOR flash.” Added bitstream property names. Added KU025 Differences to Introduction. Updated device resources and bitstream lengths (Differences in 3D ICs, Table 1, and Table 2). Added Design Tools to Introduction. Added STARTUPE3 Connections to Dedicated Pins to Design Entry. Added BSPI_READ and FALL_Edge commands to Frame Address Register (00001). Added bitstream properties to Configuration Options Register 0 (01001) and Configuration Options Register 1 (01110). Added Readback Capture to Readback Verification and CRC. Added Ganged Asynchronous BPI Configuration to Configuring Multiple FPGAs. Made minor clarifications throughout document.
03/31/2015 Version 1.3
General updates	Added configuration information for Kintex UltraScale devices XCKU085 and XCKU095. Modified Table 1 and Table 2. Clarified recommended external pull-up/down resistor values for pins M[2:0], PROGRAM_B, INIT_B, DONE, PUDC_B, BPI (FCS_B), and BPI (ADV_B) in Configuration Pins. Clarified descriptions for CFGBVS in Configuration Pins. Deleted Note 3 from Master SPI Interface, Master SPI Quad (x4), Slave Serial Configuration, Master BPI Synchronous Read, Master BPI Asynchronous Read, Single Device SelectMAP Configuration Using Boundary-Scan Configuration in UltraScale FPGAs and Parallel Configuration Modes. Changed VCCO_0 resistor value from 330Ω to 4.7 kΩ in various figures: Master SPI Interface, Slave Serial Configuration, Master BPI Synchronous Read, Master BPI Asynchronous Read, Single Device SelectMAP Configuration, Using Boundary-Scan Configuration in UltraScale FPGAs, and Parallel Configuration Modes. Clarified USR_ACCESSE2. Added note to Files for Serial Daisy Chains. Updated word counts in Bitstream Composition. Changed bit 23 from “Reserved” to “CAPTURE” in Boot History Status Register (10110). Added tables to Control Register 1 (11000). Updated word counts in Configuration Register Read Procedure (SelectMAP).
02/20/2015 Version 1.2
General updates	Added reference to PG156 under Differences from Previous Generations. Added “Production IDCODE Revision” column to Table 1. Expanded Note 2 in Configuration Interfaces. Added Persist Option and reference to Configuration Pins. Made minor clarifications to descriptions in Configuration Pin Definitions. Added last sentence in fourth paragraph under Configuration Banks Voltage Select. Modified Note 2 and added Note 3 to Table 2. Deleted clock source specification from External Master Configuration Clock (EMCCLK) Option and referenced the specification. Changed VCCO_65 destination from VCCO_0 to VCCO_65 in Master SPI Interface and Master SPI Quad (x4). Added second sentence following Figure 1 and last sentence under Synchronous Read Sequence. Updated Figure 1. Made minor clarifications to notes relevant to figures in Master BPI Synchronous Read, Synchronous Read Sequence, Using Boundary-Scan Configuration in UltraScale FPGAs,and Serial Configuration Modes. Clarified second paragraph under Shift-Dr, Exit1-DR, Pause-DR, Exit2-DR, and Update-DR. Made minor clarifications to Table 1. Clarified first paragraph under Using Boundary-Scan Configuration in UltraScale FPGAs. Clarified ICAPE3 Resources. Added Rolling Keys section. Added “Important” note to Loading Encrypted Bitstreams. Added last sentence under RSA Authentication. Clarified descriptions in OTP eFUSE Registers. Added “RMA Impact” column to Table 3. Clarified figure Identifier Value and Operation. Clarified JTAG Access to Device Identifier. Clarified Clear Configuration Memory (Step 2, Initialization). Added I/O Transition at the End of Startup. Expanded description for RS_TS_B in Configuration Options Register 1 (01110). Clarified BPI – Hardware RS Pin Design Considerations. Changed “PROGRAM_B” to “INIT_B” in Ganged Serial Configuration.
11/10/2014 Version 1.1
General updates	Updated Table 1 and Table 1. Added last paragraph under A High-Speed Configuration Option. Updated pin descriptions in Configuration Pin Definitions. Clarified External Master Configuration Clock (EMCCLK) Option. Updated Table 1. Updated pin descriptions in Pin Descriptions. Updated eFUSE. Added Configuration Details through Configuration Debugging.
12/10/2013 Version 1.0
Initial AMD release.	N/A

Revision History - Revision History - UG570

UltraScale Architecture Configuration User Guide (UG570)