Although configuration is typically a one-time event, independent of the FPGA operation, configuration choices can affect design options. Consider configuration decisions early in the design cycle to eliminate challenges late in your design cycle.
- Determine which configuration mode is optimal based upon the system's characteristics.
- Allow for JTAG configuration as an additional mode for debugging purposes.
- Provide easy access to the configuration control and status pins for debugging.
- Plan for the multi-function pins that are active during configuration and accordingly, check for conflicts with the other uses of these pins.
- Provide quality signal integrity for key signals during PCB layout including the configuration clock, even though configuration can operate at a low frequency.
- Consider all aspects of the configuration sequence to reduce configuration time, including the power-up time for the supplies.
- Consider the variety of options when generating the configuration bitstream and check for device operation conflicts.
- Inform the AMD tools via the CONFIG_VOLTAGE, CFGBVS (UltraScale FPGAs only), and CONFIG_MODE properties in your design constraint file.
- Generate the configuration bitstream using the latest version of the AMD tools targeting the version of the device that will be used (ES or production).
Important: Bitstreams generated for an
engineering sample should not be used in production devices.
Production devices must always use bitstreams with the correct
production device target.
- Correct DRC errors and review any warnings when the configuration bitstream is generated.
- Determine if remote upgrade will be needed and plan for it. See SPI Flash Programming Including Bitstream Revision Selection Application Note (XAPP1191).