RDWR_B - RDWR_B - UG570

UltraScale Architecture Configuration User Guide (UG570)

Document ID
UG570
Release Date
2025-03-04
Revision
1.20.1 English

RDWR_B is an input to the FPGA that controls whether the data pins are inputs or outputs:

  • If RDWR_B = 0, the data pins are inputs (writing to the FPGA).
  • If RDWR_B = 1, the data pins are outputs (reading from the FPGA).

For configuration, RDWR_B must be set for write control (RDWR_B = 0). For readback, RDWR_B must be set for read control (RDWR_B = 1) while CSI_B is asserted.

3D ICs do not support the ABORT sequence. In monolithic devices, changing the value of RDWR_B from Low to High while CSI_B is Low triggers an ABORT, and the configuration I/O changes from input to output asynchronously. The ABORT status appears on the data pins synchronously. Changing the value of RDWR_B from High to Low while CSI_B is Low also triggers an ABORT, and the configuration I/O changes from output to input asynchronously with no ABORT status readback. If readback is not needed, RDWR_B can be tied to ground or used for debugging with SelectMAP ABORT.

The RDWR_B signal is ignored while CSI_B is de-asserted. Read/write control of the 3-stating of the data pins is asynchronous. The FPGA actively drives SelectMAP data without regard to CCLK if RDWR_B is set for read control (RDWR_B = 1, Readback) while CSI_B is asserted.