At power on, a race condition between the FPGA and parallel NOR flash can exist because they can be supplied by different power rails or because they can respond at different times along the ramp of a shared power supply. Special attention to the FPGA and parallel NOR flash power-on sequence or power-on ramps is essential. The parallel NOR flash interface signals are within FPGA dedicated bank 0 and I/O bank 65.
The FPGA sends the address to the parallel NOR flash to acquire the bitstream after the FPGA has completed its power-on reset sequence. The parallel NOR flash is not ready to receive an address until the parallel NOR flash power-on reset sequence has completed. Under specific conditions when the VCC power supply to the parallel NOR flash powers up after the FPGA VCCINT and VCCAUX power supplies, the FPGA address counter can pass the critical start of the bitstream within the parallel NOR flash before the flash becomes responsive. The system must be designed such that the parallel NOR flash is ready to receive the address before the FPGA sends the address. For more details, see Power-On Sequence Precautions for Flash.