At power-on, the FPGA automatically starts its configuration procedure. When the FPGA is in a master configuration mode, the configuration flash must be awake and ready to receive commands and/or clocks before the FPGA begins sending them. Because different power rails can supply the FPGA and flash or because the FPGA and flash can respond at different times along the ramp of a shared power supply, special attention to the FPGA and flash power-on sequence or power-on ramps is essential. The power-on sequence or power supply ramps can cause the FPGA to awaken or start before the flash, or vice versa. In addition, some flash devices specify a minimum time period, which can be several milliseconds from power-on, during which the device must not be selected. For many systems with near-simultaneous power supply ramps, the default FPGA power-on reset time (TPOR) can sufficiently delay the start of the FPGA configuration procedure such that the flash becomes ready before the start of the FPGA configuration procedure.
In general, the system design must consider the effect of the power sequence, the power ramps, FPGA power-on reset timing, and flash power-up timing on the timing relationship between the start of FPGA configuration and the readiness of the flash. Refer to the AMD data sheet for FPGA power supply requirements and timing, and check the flash data sheet for the flash power-up timing requirements.
One of these system design approaches can ensure that the flash is ready to receive commands before the FPGA starts its configuration procedure:
- Control the sequence of the power supplies such that the flash is certain to be powered and ready before the FPGA begins its configuration procedure.
- Use the longer TPOR
delay by connecting
POR_OVERRIDEto GND. - Hold the FPGA
INIT_Bpin Low from power-up to delay the start of the FPGA configuration procedure. Release theINIT_Bpin to High after the flash becomes ready.