Pin Descriptions - Pin Descriptions - UG570

UltraScale Architecture Configuration User Guide (UG570)

Document ID
UG570
Release Date
2025-03-04
Revision
1.20.1 English

The following table describes the USR_ACCESSE2 primitive pins.

Table 1. USR_ACCESSE2 Pin Descriptions
Pin Type Width Description
CFGCLK Output 1 Configuration Clock
DATA[31:0] Output 32 Configuration Data reflecting the contents of the AXSS register
DATAVALID Output 1 Active-High Data Valid