Parallel Daisy Chain Configuration - Parallel Daisy Chain Configuration - UG570

UltraScale FPGA configuration supports a parallel daisy-chain. The following figure shows an example schematic of the leading device in BPI mode. The leading device can also be in master or slave SelectMAP modes. The D[15:00], CCLK, RDWR_B, PROGRAM_B, DONE, and INIT_B pins share a common connection between all of the devices. The CSI_B pins are daisy chained.

Notes relevant to the previous figure:

1. The DONE pin is by default an open-drain output. See Configuration Pin Definitions for DONE signal details.
2. The INIT_B pin is a bidirectional, open-drain pin. An external pull-up is required.
3. The FCS_B, FWE_B, FOE_B, CSO_B weak pull-up resistors should be enabled, otherwise external pull-up resistors are required for each pin. By default, all dual-mode I/Os have weak pull-downs after configuration.
4. The first device in the chain can be master SelectMAP, slave SelectMAP, or BPI. See Figure 1 for a more detailed view of the BPI connections.
5. Readback in the parallel daisy chain scheme is not supported.
6. Fallback MultiBoot is not supported in this configuration.