Parallel Bus Bit Order - Parallel Bus Bit Order - UG570

UltraScale Architecture Configuration User Guide (UG570)
Document ID
UG570
Release Date
2025-03-04
Revision
1.20.1 English

Traditionally, in SelectMAP x8 mode, configuration data is loaded one byte per CCLK, with the most significant bit (MSB) of each byte presented to the D0 pin. Although this convention (D0 = MSB, D7 = LSB) differs from many other devices, it is consistent across all AMD FPGAs. The bit swap rule also applies to BPI x8 modes and to the ICAPE3 interface (see Bit Swapping). The bit swap rule is extended to x16 and x32 bus widths, that is, the data is bit swapped within each byte.

The following two tables show examples of a Sync word 0xAA995566 inside a bitstream (see Sync Word). These examples illustrate what is expected at the FPGA data pins when using parallel configuration modes, such as slave SelectMAP, master SelectMAP, and BPI modes, and when using the ICAPE3 interface.

Table 1. Sync Word Bit Swap Example
Sync Word [31:24] 1 [23:16] [15:8] [7:0]
Bitstream Format 0xAA 0x99 0x55 0x66
Bit Swapped 0x55 0x99 0xAA 0x66
  1. [31:24] changes from 0xAA to 0x55 after bit swapping.
Table 2. Sync Word Data Sequence Example for x8, x16, and x32 Modes
CCLK Cycle 1 2 3 4
D[7:0] pins for x8 0x55 0x99 0xAA 0x66
D[15:0] pins for x16 0x5599 0xAA66 ... ...
D[31:0] pins for x32 0x5599AA66 ... ... ...