Packet Types - Packet Types - UG570

UltraScale Architecture Configuration User Guide (UG570)
Document ID
UG570
Release Date
2025-03-04
Revision
1.20.1 English

The FPGA bitstream consists of two packet types: Type 1 and Type 2. These packet types and their use are described in this section.

Type 1 Packet

The Type 1 packet is used for register reads and writes. Only five out of 14 register address bits are used. The header section is always a 32-bit word.

Following the Type 1 packet header is the Type 1 data section, which contains the number of 32-bit words specified by the word count portion of the header. See the following tables.

Table 1. Type 1 Packet Header Format
Header Type Opcode Register Address Reserved Word Count
[31:29] [28:27] [26:13] [12:11] [10:0]
001 xx RRRRRRRRRxxxxx RR xxxxxxxxxxx
  1. “R" means the bit is not used and reserved for future use. The reserved bits should be written as 0s.
Table 2. OPCODE Format
OPCODE Function
00 NOOP
01 Read
10 Write
11 Reserved

Type 2 Packet

The Type 2 packet, which must follow a Type 1 packet, is used to write long blocks. No address is presented here because it uses the previous Type 1 packet address. The header section is always a 32-bit word.

Following the Type 2 packet header is the Type 2 Data section, which contains the number of 32-bit words specified by the word count portion of the header. See the following table.

Table 3. Type 2 Packet Header
Header Type Opcode Word Count
[31:29] [28:27] [26:0]
010 xx xxxxxxxxxxxxxxxxxxxxxxxxxx