This user guide describes the configuration methods and features for the Artix UltraScale+, Kintex UltraScale, Kintex UltraScale+, Virtex UltraScale, and Virtex UltraScale+ FPGAs.
AMD FPGAs are highly flexible, reprogrammable logic devices. Like processors, AMD FPGAs are fully user programmable. For FPGAs, the program is called a bitstream, which defines the application-specific FPGA functionality. The bitstream loads into the FPGA internal memory at system power-up or on demand by the system.
Like processors and processor peripherals, AMD FPGAs can be reprogrammed, in system, on demand, an unlimited number of times. After programming, the FPGA bitstream is stored in highly robust CMOS configuration latches (CCLs). Although CCLs are reprogrammable like SRAM, CCLs are designed primarily for data integrity. Because the AMD FPGA bitstream is stored in CCLs, the device must be reconfigured after it is power cycled.
The process whereby the defining data is loaded or programmed into the FPGA is called configuration. Configuration is designed to be flexible to accommodate different application needs and, wherever possible, to leverage existing system resources to minimize system costs.
Similar to processors, AMD FPGAs optionally load or boot themselves automatically from an external nonvolatile memory device. Alternatively, similar to processor peripherals, AMD FPGAs can be downloaded or programmed by an external device, such as a microprocessor, DSP processor, microcontroller, PC, or board tester. The configuration datapath can be serial to minimize pin requirements, including configuration through the industry-standard IEEE 1149.1 JTAG boundary scan interface. A parallel configuration datapath provides maximum performance and access to industry-standard interfaces, ideal for external data sources like processors, or x8- or x16-parallel flash memory.
The configuration bitstream is loaded into the FPGA through special configuration pins. These configuration pins serve as the interface for a number of different configuration modes:
- Slave serial
- Slave SelectMAP (parallel) (x8, x16, and x32)
- JTAG boundary scan
- Master serial peripheral interface (SPI) (serial NOR flash x1, x2, x4, and dual x4, effectively x8)
- Master byte peripheral interface (BPI) (parallel NOR flash x8 and x16)
- Master serial
- Master SelectMAP (parallel) (x8 and x16)
The terms master and slave refer to the
direction of the configuration clock (CCLK):
- In master configuration modes, the FPGA
drives
CCLKfrom an internal oscillator. Configuration options are used to select the desired frequency. After configuration, theCCLKis turned off by default, and theCCLKpin is 3-stated with a weak pull-up. - In slave configuration modes,
CCLKis an input.
The specific configuration mode is selected
by setting the appropriate level on the mode input pins
M[2:0]. The M2,
M1, and M0 mode pins should be set
at a constant DC voltage level, either through pull-up or pull-down
resistors (<1 kΩ ), or tied directly to ground or VCCO_0. The JTAG (boundary scan) configuration interface is
always available, regardless of the mode pin settings.
The configuration modes are explained in detail in Master SPI Configuration Mode through SelectMAP Configuration Modes.
The FPGA can also control its own configuration through internal connections from the FPGA logic to the configuration logic. The device can be either fully reprogrammed with an alternative design it has selected, or partial reconfiguration allows specific regions of the FPGA to be reprogrammed with new functionality while applications continue to run in the remainder of the device.