| Register Name | Size (Bits) | Contents | Description |
|---|---|---|---|
| FUSE_RSA | 384 |
Bitstream authentication key [383:0] (bit 0 shifted first) |
Stores an SHA-3 hash of the public key used for RSA bitstream authentication. |
| FUSE_KEY | 256 |
Bitstream encryption key [255:0] (bit 0 shifted first) |
Stores a key for use by AES-GCM bitstream decryption and authentication. The eFUSE key can be used instead of the key stored in battery-backed RAM. |
| FUSE_DNA | 96 |
Device identifier programmed by AMD [95:0] (bit 0 shifted first) |
Unique device identifier bits [95:0], corresponding to the 96-bit read-only DNA_PORTE2 primitive value known as Device DNA. See Device Identifier (Device DNA). |
| FUSE_USER | 32 |
User defined [31:0] (bit 0 shifted first) |
Stores a 32-bit user-defined code. This register is readable from the FPGA logic using the EFUSE_USR primitive (see Design Entry). Depending on the read/write access bits in the CNTL register, the code can be programmed and read through the JTAG port. |
| FUSE_USER_128 | 128 |
User defined [127:0] (bit 0 shifted first) |
Stores a 128-bit user-defined code. This register is readable from the JTAG FUSE_USER_128 instruction. The JTAG FUSE_USER_128 data register length is 384 bits in UltraScale FPGAs or 176 bits in UltraScale+ FPGAs. Only bits [127:0] are supported for user code storage, and the remaining bits are reserved and can be any value. |
| FUSE_CNTL | 21 |
Control Bits [20:0] (bit 0 shifted first) |
In UltraScale FPGAs this controls key use and read/write access to eFUSE registers. This register can be programmed and read through the JTAG port. |
| 24 |
Control Bits [23:0] (bit 0 shifted first) |
In UltraScale+ FPGAs this key use and read/write access to eFUSE registers. This register can be programmed and read through the JTAG port. | |
| FUSE_SEC | 32 |
Security Control Bits [31:0] (bit 0 shifted first) |
Controls encryption and authentication options. Depending on the read/write access bits in the CNTL register, this register can be programmed and read through the JTAG port. |
In addition to eFUSE registers used by the FPGA for
security settings and selected other options, there are user-accessible eFUSE registers
controlled by JTAG instructions. The following table lists the eFUSE registers with their
sizes and usage.
Note: because these registers store values using
eFUSE bits, they can only be programmed once.