Multiple Device SelectMAP Configuration - Multiple Device SelectMAP Configuration - UG570

Multiple UltraScale FPGAs in slave SelectMAP mode can be connected on a common SelectMAP bus (see the following figure). In a SelectMAP bus, the DATA, CCLK, RDWR_B, PROGRAM_B, DONE, and INIT_B pins share a common connection between all of the devices. To allow each device to be accessed individually, the CSI_B (chip select) inputs must not be tied together. External control of the CSI_B signal is required and is usually provided by a microprocessor or CPLD.

If Readback is going to be performed on the device after configuration, the RDWR_B signal must be handled appropriately. (For details, refer to Readback Verification and CRC.)

Otherwise, RDWR_B can be tied Low. Refer to Bitstream Loading (Steps 4-7).

Notes relevant to the previous figure:

1. The DONE pin is by default an open-drain output. See Configuration Pin Definitions for DONE signal details.
2. The INIT_B pin is a bidirectional, open-drain pin. An external pull-up resistor is required.
3. An external controller such as a microprocessor or CPLD is needed to control configuration.
4. The data bus can be x8, x16, or x32 (for slave SelectMAP).
5. See Figure 1 for a more detailed view of the slave SelectMAP connections.