It is possible to configure multiple UltraScale FPGAs in a chain (see Figure 2). The devices in
the JTAG chain are configured one at a time. The multiple device configuration
steps can be applied to any size chain as long as excellent signal integrity is
maintained. The configuration tools automatically discover the devices in the
chain, starting from the one nearest to TDI coming from the JTAG
header. If JTAG is the only configuration mode, then PROGRAM_B,
INIT_B, and DONE can each be connected to
separate pull-up resistors.
Refer to the state diagram in Figure 2 for the following TAP controller steps:
- On power-up, place a logic
1on theTMSand clock theTCKfive times. This ensures starting in the TLR (Test-Logic-Reset) state. - Load the
CFG_INinstruction into the target device (and BYPASS in all other devices). - Go through the RTI state (RUN-TEST/IDLE).
- Load in the configuration bitstream per steps 13 through 17 in the previous table.
- Repeat step 2 and step 3 for each device.
- Load the
JSTARTcommand into all devices. - Go to the RTI state and clock TCK 2,000 times.
All devices are active at this point.