UltraScale FPGAs can be daisy-chained with earlier 7 series families. There are four important design considerations when designing a mixed serial daisy chain:
- Select a CCLK frequency that is compatible with all devices in the daisy chain.
- UltraScale architecture-based FPGAs should always be at the beginning of the serial daisy chain, with 7 series devices located at the end of the chain.
- All UltraScale architecture-based FPGAs have similar bitstream options. The guidelines provided for UltraScale architecture-based FPGAs bitstream options should be applied to all devices in a serial daisy chain, when possible.
- The number of configuration bits that a device can pass through its DOUT pin is limited. For UltraScale architecture-based FPGAs and 7 series FPGAs, the limit is 4,294,967,264 bits. The sum of the bitstream lengths for all downstream devices must not exceed this number.