The master serial configuration mode is the
same as the slave serial configuration mode, except that the FPGA generates the
CCLK. That is, the CCLK is an output in master serial
mode. Master serial mode is not recommended for new designs.
The AMD Kintex™
UltraScale™
and AMD Virtex™
UltraScale™
FPGAs support master serial mode for configuration from legacy serial PROMs (when applicable)
or for custom, CPLD-based configuration state machines driven by the FPGA
CCLK. The AMD Artix™
UltraScale+™
,
Kintex UltraScale+, and Virtex UltraScale+ FPGAs do not support master serial mode. AMD Platform Flash PROMs do not support UltraScale
architecture-based FPGAs.