Master SPI Read Commands - Master SPI Read Commands - UG570

The master SPI configuration mode supports the read operations listed in the following table. When starting the master SPI configuration mode, the UltraScale and UltraScale+ FPGAs clock data out on the falling edge to transmit the Fast Read opcode (0Bh ) with a 24-bit address of 0 to the flash. A bitstream loaded at address 0 in the primary flash can contain FPGA commands in the initial part of the bitstream that causes the configuration logic to issue one of the supported SPI instructions listed in the following table. If the SPI command is for x1, x2, or x4 configuration, the FPGA then issues a new read command for the Fast Read (0Bh), Dual Output Fast Read (3Bh), or Quad Output Fast Read (6Bh) or the equivalent 32-bit address version (0Ch, 3Ch, or 6Ch respectively) to the primary flash. If the instruction starts the master SPI x8 configuration sequence, the Quad Output Fast Read (6Bh), or Quad Output Fast Read, 32-bit address (6Ch) read command is issued to both the primary and secondary flashes simultaneously. The Vivado Configuration Dialog programming tools are used to enable the new widths and 32-bit addressing commands in the bitstream.