Master SPI Quad (x4) - Master SPI Quad (x4) - UG570

UltraScale FPGAs support a x4 quad SPI master configuration width as shown in the following figure.

Notes relevant to the previous figure:

1. The DONE pin is by default an open-drain output. See Configuration Pin Definitions for DONE signal details.
2. The INIT_B pin is a bidirectional, open-drain pin. An external pull-up resistor is required.
3. CCLK signal integrity is critical.
4. Daisy-chaining is not supported for x2, x4, or x8 master SPI configuration modes.
5. A series resistor should be considered for the datapath from the flash to the FPGA to minimize overshoot. The proper resistor value can be determined from simulation.
6. The FPGA V_{CCO_0} supply must be compatible with the V_CC for the I/O of the flash device.
7. Data is clocked out of the flash on the CCLK falling edge and clocked in on the FPGA on the rising edge, unless negative edge clocking is enabled in the Vivado Configuration Dialog box.
8. The CCLK frequency is adjusted by the Vivado Configuration Rate bitstream setting (BITSTREAM.CONFIG.CONFIGRATE) if the source is the internal oscillator. Alternatively, the Enable External Configuration Clock option (BITSTREAM.CONFIG.EXTMASTERCCLK_EN) can switch the CCLK to source from the EMCCLK pin to use an external clock source. See EMCCLK Option and File Generation for details.
9. The FPGA PUDC_B pin is tied to GND to enable internal pull-ups or it can be tied to V_{CCO_0} to 3-state the SelectIO pins after power-up and during configuration. See Configuration Pin Definitions for PUDC_B signal details.