Master SPI Interface - Master SPI Interface - UG570

The master SPI configuration mode reads from standard 1-bit serial NOR flash, and can optionally read from flash devices that support x2 and x4 Fast Output Read operations. UltraScale FPGAs also provide a x8 master SPI configuration mode by connecting to two identical flash memories that contain the bitstream split across both devices. These modes are proportionally faster than the standard 1-bit SPI interface and are selected with the bitstream option BITSTREAM.CONFIG.SPI_BUSWIDTH. In addition, a negative edge clocking mode (BITSTREAM.CONFIG.SPI_FALL_EDGE) is available to make better use of the entire clock period and allow higher configuration speed. The master SPI configuration interface is represented in the following figure.

The following figure shows the connections for a SPI configuration with a x1 or x2 data width. These connections are the same because the x2 mode uses the D[00] pin as a dual-purpose Data In/Out pin. The data pins used only as FPGA inputs are shown as unidirectional in the figures, although in some cases they might be bidirectional before or after configuration. Daisy-chained configuration mode is only available in SPI x1 mode. The FPGA pin connections to the serial NOR flash involved in the master SPI mode are listed in Configuration Pins.

Notes relevant to the previous figure:

1. The DONE pin is by default an open-drain output. See Configuration Pin Definitions for DONE signal details.
2. The INIT_B pin is a bidirectional, open-drain pin. An external pull-up resistor is required. See Configuration Pin Definitions for INIT_B signal details.
3. CCLK signal integrity is critical.
4. DOUT should be connected to the DIN of the downstream FPGA for daisy-chained SPI x1 configuration mode. Daisy-chaining is not supported for x2, x4, or x8 master SPI configuration modes.
5. A series resistor should be considered for the datapath from the flash to the FPGA to minimize overshoot. The proper resistor value can be determined from simulation.
6. The FPGA V_{CCO_0} supply must be compatible with the V_CC for the I/O of the flash device.
7. Data is clocked out of the flash on the CCLK falling edge and clocked in on the FPGA on the rising edge, unless negative edge clocking is enabled in the AMD Vivado™ Edit Device Properties dialog.
8. The CCLK frequency is adjusted by the Vivado Configuration Rate bitstream setting (BITSTREAM.CONFIG.CONFIGRATE) if the source is the internal oscillator. Alternatively, the Enable External Configuration Clock option (BITSTREAM.CONFIG.EXTMASTERCCLK_EN) can switch the CCLK to source from the EMCCLK pin to use an external clock source. See EMCCLK Option and File Generation for details.
9. The FPGA PUDC_B pin is tied to GND to enable internal pull-ups or it can be tied to V_{CCO_0} to 3-state the SelectIOpins after power-up and during configuration. See Configuration Pin Definitions for PUDC_B signal details.

The Vivado tools provide control of configuration bitstream options through Tcl command line properties, and also provides support through a configuration dialog box. After loading a design, you can select Tools > Edit Device Properties to edit programming and configuration properties in the Edit Device Properties dialog box. For more details, see Vivado Design Suite User Guide: Programming and Debugging (UG908).

The Vivado tools provide the ability to program a serial flash using an indirect programming method. This downloads a new FPGA design that provides a connection from the Vivado tools through the FPGA to the flash. Previous FPGA memory contents are lost during this operation. For the specific densities supported by the programming tools, consult Vivado Design Suite User Guide: Programming and Debugging (UG908).

For additional details on the SPI x1, x2, and x4 operation, including programming instructions, see SPI Configuration and Flash Programming in UltraScale FPGAs (XAPP1233). The SPI x1 mode sequence diagram is shown in the following figure.

Notes relevant to the previous figure:

• Waveforms represent the relative sequence of events and are not to scale. See the flash memory data sheet for detailed SPI command and data timing.