Master SPI Dual Quad (x8) - Master SPI Dual Quad (x8) - UG570

UltraScale architecture-based FPGAs introduce a master SPI x8 configuration width that uses two identical x4 SPI flash devices connected in a parallel fashion as shown in the following figure. The clock, CCLK, is common for both flash devices with the select and data pins being separate, but identically driven when x8 mode is used.

Notes relevant to the previous figure:

1. The DONE pin is by default an open-drain output. See Configuration Pin Definitions for DONE signal details.
2. The INIT_B pin is a bidirectional, open-drain pin. An external pull-up resistor is required.
3. CCLK signal integrity is critical.
4. Daisy-chaining is not supported for x2, x4, or x8 master SPI configuration modes.
5. A series resistor should be considered for the datapath from the flash to the FPGA to minimize overshoot. The proper resistor value can be determined from simulation.
6. The FPGA V_{CCO_0} supply must be compatible with the V_CC for the I/O of the flash.
7. Data is clocked out of the flash on the CCLK falling edge and clocked in on the FPGA on the rising edge, unless negative edge clocking is enabled in the Vivado Configuration Dialog.
8. The CCLK frequency is adjusted by the Configuration Rate option if the source is the internal oscillator. Alternatively, the Enable External Configuration Clock option can switch the CCLK to source from the EMCCLK pin to use an external clock source.
9. The FPGA PUDC_B pin is tied to GND to enable internal pull-ups or it can be tied to V_{CCO_0} to 3-state the SelectIOpins after power-up and during configuration. See Configuration Pin Definitions for PUDC_B signal details.

To generate a bitstream for x8 SPI mode, the bitstream should be generated with the property CONFIG_MODE to SPIx8. For x8 SPI configuration, the primary flash must contain the initial portion of a configuration bitstream that includes the x8 SPI configuration command. When the FPGA reads in this command, it will issue either Quad Output Fast Read (6Bh) or Quad Output Fast Read, 32-bit address (6Ch) simultaneously to both the primary and secondary flash memories. The secondary flash should contain dummy information that is equal in size to the initial portion of the bitstream in the primary flash. Beginning at the next address after the initial portion of the bitstream in the primary flash and after the dummy data in the secondary flash, the configuration bitstream is split evenly between the flash devices beginning with the first four bits in the primary flash and the next four bits in the secondary flash. The entire configuration bitstream will then be split between the two flash devices with the least significant nibble of each byte in the primary flash and the most significant nibble at the same address in the secondary flash.

The x8 SPI master configuration mode requires that the flash devices be identical and identically configured. For example, some flash devices have programmable latency or dummy cycles via nonvolatile configuration bits that might need to be set to allow high clock rates for the read commands. The latency cycles must be the same between the primary and secondary flash devices to maintain bit alignment.