The self-loading FPGA configuration modes, generically called master modes, are available with either a serial or parallel datapath. In master mode, the FPGA's configuration bitstream typically resides in nonvolatile memory on the same board. The FPGA internally generates a configuration clock signal called CCLK, and the FPGA controls the configuration process by sending a clock or addresses to the flash memory. See the following figure.
Figure 1. Master Configuration Modes
