Master BPI Synchronous Read - Master BPI Synchronous Read - UG570

The UltraScale architecture-based FPGAs master BPI configuration mode can read a bitstream from select parallel NOR devices that support burst, synchronous reads. The master BPI configuration mode with synchronous read is the fastest direct flash configuration option for UltraScale architecture-based FPGAs without the need for customized external control logic.

The following figure provides the connectivity diagram between the FPGA and parallel NOR flash for the master BPI configuration mode to support the synchronous read and the EMCCLK (external master configuration clock). Refer to External Master Configuration Clock (EMCCLK) Option for configuration clock option details. The following figure supports both synchronous and asynchronous read modes. If only asynchronous mode is required for the application, refer to Figure 1 for connections that are optional.

Figure 1. Master BPI Configuration Interface Example for x16 Synchronous Read

Notes relevant to the previous figure:

1. The DONE pin is by default an open-drain output. See Configuration Pin Definitions for DONE signal details.
2. The INIT_B pin is a bidirectional, open-drain pin. An external pull-up resistor is required. See Configuration Pin Definitions for INIT signal details.
3. CCLK signal integrity is critical.
4. For the synchronous read example the x16 data bus interface is supported. x8 data bus interface is only supported in asynchronous read mode.
5. CSO_B should be connected to the CSI_B of the downstream FPGA for parallel daisy-chains.
6. The FPGA V_{CCO_0} supply must be compatible with the supply voltage for the I/O of the selected parallel NOR device.
7. The CCLK frequency is adjusted by the Vivado Configuration Rate bitstream setting (BITSTREAM.CONFIG.CONFIGRATE) if the source is the internal oscillator. Alternatively, the Enable External Configuration Clock option (BITSTREAM.CONFIG.EXTMASTERCCLK_EN) can switch the CCLK to source from the EMCCLK pin to use an external clock source. See EMCCLK Option and File Generation for details.
8. The FPGA PUDC_B pin is tied to GND to enable internal pull-ups or it can be tied to V_{CCO_0} to 3-state the SelectIO pins after power-up and during configuration. See Configuration Pin Definitions for PUDC_B signal details.
9. See the respective data sheet (see Kintex UltraScale FPGAs Data Sheet: DC and AC Switching Characteristics (DS892) or Virtex UltraScale FPGAs Data Sheet: DC and AC Switching Characteristics (DS893)) for the V_CCINT, V_CCAUX, and V_{CCO_0} supply voltages.
10. The ADV_B and CCLK connections are required for synchronous read operation, but these connections to the flash are optional for asynchronous read mode. The CCLK output is not used to connect to flash in the asynchronous read mode, but it is used to sample flash read data during configuration. All timing is referenced to CCLK. On setups only targeting asynchronous read, the flash ADV_B and CLK lines must be tied to GND.
11. The RS[1:0] pins are not connected, as shown in the previous figure. This sample schematic supports single bitstream configuration. These output pins are optional and can be used for MultiBoot configuration.
12. The JTAG connections are shown for a simple, single-device JTAG scan chain. When multiple devices are on the JTAG scan chain, use the proper IEEE Std 1149.1 daisy-chain technique to connect the JTAG signals. The TCK signal integrity is critical for JTAG operation. Route, terminate, and if necessary, buffer the TCK signal appropriately to ensure signal integrity for the devices in the JTAG scan chain.