Master BPI Interface - Master BPI Interface - UG570

The master BPI configuration mode supports parallel NOR flash read options: x16 synchronous and x8/x16 asynchronous. By default, the master BPI configuration mode uses the x8 asynchronous parallel NOR flash read option. For applications that require faster configuration times, the x16 data bus width with synchronous read option should be enabled as described in See File Generation.

The master BPI configuration interface is represented in the following figure. Detailed connections between the FPGA and the parallel NOR flash for master BPI configuration mode are shown in Master BPI Synchronous Read and Master BPI Asynchronous Read. The FPGA signals are defined in Configuration Pin Definitions.

Parallel NOR flash is a popular option for storing and delivering the bitstream because the wide x16 data bus provides faster configuration over other flash alternatives. In addition to the faster configuration, systems that use parallel NOR flash memory for random-access, nonvolatile application data storage can also benefit from consolidating the configuration storage into a single memory device.

When choosing a parallel NOR flash for the configuration storage several factors should be considered:

• The storage capacity required by the application (current and migration options)
• The data bus width options for reduced configuration time
• The flash I/O voltage range

Refer to Table 1 for information on the bitstream size to determine the minimum flash density required for configuration. The configuration pins in bank 0 and the multi-purpose pins in bank 65 are used by the master BPI configuration mode interface and must receive the same V_CCO voltage and be compatible with the parallel NOR flash I/O specification. The flash data sheet should be reviewed carefully to ensure the feature and voltage requirements are supported.

Parallel NOR flash examples are provided in this section for Synchronous and Asynchronous read options. See Vivado Design Suite User Guide: Programming and Debugging (UG908) for details for flash families that are supported and can be indirectly programmed using AMD Vivado™ tool device programmer.

The following table provides an overview of the UltraScale architecture-based FPGAs feature support with the flash read options. Refer to See Master BPI Synchronous Read and Master BPI Asynchronous Read for details.