Master BPI Asynchronous Read - Master BPI Asynchronous Read - UG570

By default, UltraScale FPGAs use the parallel NOR flash asynchronous read in the master BPI configuration mode. The FPGA drives the address bus from a given start address, and the flash sends back the bitstream data. The default start address is address 0, but the start address can be explicitly set in a MultiBoot reconfiguration procedure. In asynchronous read mode, supported bus widths of x8 and x16 are auto-detected. The following figure provides the connectivity diagram between the FPGA and parallel NOR flash for the x16 asynchronous read master BPI configuration mode.

Notes relevant to the previous figure:

1. Parallel NOR flash that have a BYTE# signal must set the BYTE# signal appropriately. For x16 data bus width the BYTE# signal must be set High. For x8 data bus width the BYTE# signal must be set Low. Refer to the flash data sheet for details.
2. Review the flash vendor's data sheet carefully to ensure that the flash LSB address signal is connected correctly depending on the vendor and data bus width used. Parallel NOR flash with the dual purpose DQ15/A-1 signal must ensure that it is connected properly. The DQ15/A-1 is a data pin in x16 mode. For the x8 mode the flash DQ15/A-1 is an LSB address line and needs to be connected to the FPGA A00..
3. The DONE pin is by default an open-drain output. See Configuration Pin Definitions for DONE signal details.
4. The INIT_B pin is a bidirectional, open-drain pin. An external pull-up resistor is required. See Configuration Pin Definitions for INIT signal details.
5. The x16 BPI interface is shown in the previous figure. For x8 BPI interfaces, only D[07:00] are used.
6. The flash vendor data sheet should be referred to for flash signal connectivity details. Ensure the FPGA LSB A00 is aligned to the flash LSB address (dependent on the flash family and data width selected).
7. CSO_B should be connected to the CSI_B of the downstream FPGA for parallel daisy-chains.
8. The FPGA V_{CCO_0} supply must be compatible with the V_CC for the I/O of the selected parallel NOR device.
9. The CCLK frequency is adjusted by the Vivado Configuration Rate bitstream setting (BITSTREAM.CONFIG.CONFIGRATE) if the source is the internal oscillator. Alternatively, the Enable External Configuration Clock option (BITSTREAM.CONFIG.EXTMASTERCCLK_EN) can switch the CCLK to source from the EMCCLK pin to use an external clock source. See EMCCLK Option and File Generation for details.
10. The FPGA PUDC_B pin is tied to GND to enable internal pull-ups or it can be tied to V_{CCO_0} to 3-state the SelectIO pins after power-up and during configuration. See Configuration Pin Definitions for PUDC_B signal details.
11. See the respective data sheet ( Virtex UltraScale FPGAs Data Sheet: DC and AC Switching Characteristics (DS893) or Kintex UltraScale FPGAs Data Sheet: DC and AC Switching Characteristics (DS892)) for the V_CCINT, V_CCAUX, and V_{CCO_0} supply voltages.
12. ADV_B and CCLK connections are available on some supported flash families, but the connections are not required for asynchronous read operation. The CCLK output is not used to connect to flash in the asynchronous read mode, but it is used to sample flash read data during configuration. All timing is referenced to CCLK. On asynchronous read setups, if the flash has ADV_B and CLK lines, they must be tied to GND.
13. The RS[1:0] pins are not connected, as shown in the previous figure. This sample schematic supports single bitstream configuration. These output pins are optional and can be used for MultiBoot configuration.
14. The JTAG connections are shown for a simple, single-device JTAG scan chain. When multiple devices are on the JTAG scan chain, use the proper IEEE Std 1149.1 daisy-chain technique to connect the JTAG signals. The TCK signal integrity is critical for JTAG operation. Route, terminate, and if necessary, buffer the TCK signal appropriately to ensure signal integrity for the devices in the JTAG scan chain.