MASTER_JTAG provides control of the JTAG port from the FPGA logic, overriding the external pins. This is a new feature in the UltraScale architecture-based FPGAs. When MASTER_JTAG is instantiated, the external JTAG port is disabled at the end of configuration startup (EOS). Therefore MASTER_JTAG should not be instantiated except for a design requiring internal access to the JTAG port. This is intended only for eFUSE programming in advanced secure applications that cannot use the standard eFUSE programming methodologies. This component can be used for AES key programming (BBRAM or eFUSE), USER eFUSE programming during runtime, or where external JTAG access is prohibited. Because the external JTAG port is disabled, MASTER_JTAG prevents the use of the Vivado device programmer and the Vivado logic analyzer. For 3D ICs, MASTER_JTAG provides access only to the SLR in which it is instantiated, with an instruction register length of 6 bits.