MASK Register (00110) - MASK Register (00110) - UG570

UltraScale Architecture Configuration User Guide (UG570)

Document ID
UG570
Release Date
2025-03-04
Revision
1.20.1 English

Writes to the CTL0 and CTL1 registers are bit-masked by the MASK register. A 1 in the MASK register allows the corresponding bit in the CTL0 or CTL1 register to be written. The default is all 0s. The MASK register must be written before each write to CTL0 or CTL1.