The FPGA internal device identifier can be read via the JTAG port using the private FUSE_DNA command. Bit 0 of the identifier, shown in Figure 1, appears on the TDO JTAG output following the FUSE_DNA command when the device enters the Shift-DR state. The remaining Device DNA bits and any data on the input to the register are shifted out sequentially while the JTAG controller is left in the Shift-DR state.
The Vivado Device Programmer also supports reading the Device DNA by viewing the eFUSE registers in the Hardware Device Properties window, or by using the following Tcl command:
report_property [lindex [get_hw_device] 0] REGISTER.EFUSE.FUSE_DNA The user-defined eFUSE register FUSE_USER can be read
similarly to FUSE_DNA, using the JTAG FUSE_USER command, the Hardware Device
Properties, or reporting the REGISTER.EFUSE.FUSE_USER
property. See
Vivado Design Suite User Guide:
Programming and Debugging (UG908) for more details.