Instruction Register - Instruction Register - UG570

UltraScale Architecture Configuration User Guide (UG570)
Document ID
UG570
Release Date
2025-03-04
Revision
1.20.1 English

The Instruction register (IR) is connected between TDI and TDO during an instruction scan sequence. In preparation for an instruction scan sequence, the Instruction register is parallel-loaded with a fixed instruction capture pattern. This pattern is shifted out onto TDO (LSB first), while an instruction is shifted into the Instruction register from TDI.

To determine the operation to be invoked, an OPCODE necessary for the UltraScale FPGA boundary-scan instruction set is loaded into the Instruction register. The IR is 6 bits wide for monolithic UltraScale FPGAs. See Table 2 for IR length for other devices. The following table describes the boundary scan instructions for UltraScale FPGAs. See the BSDL files for commands and codes for UltraScale+ FPGAs. See Table 1 for eFUSE-related instructions.

Table 1. UltraScale FPGA Boundary-Scan Instructions
Boundary-Scan Command Binary Code [5:0] 1 Description
EXTEST 100110 Enables 1149.1 boundary-scan EXTEST operation
EXTEST_PULSE 111100 Enables 1149.6 EXTEST_PULSE operation for transceivers
EXTEST_TRAIN 111101 Enables 1149.6 EXTEST_TRAIN operation for transceivers
SAMPLE/PRELOAD 000001 Enables boundary-scan SAMPLE/PRELOAD operation
USER1 000010 Access user-defined register 1
USER2 000011 Access user-defined register 2
USER3 100010 Access user-defined register 3
USER4 100011 Access user-defined register 4
USERCODE 001000 Enables shifting out user code
IDCODE 001001 Enables shifting out of IDCODE
HIGHZ_IO 001010 Disable user I/O pins only while enabling the Bypass register
BYPASS 111111 Enables BYPASS
CFG_IN 000101 Access the configuration bus for configuration
CFG_OUT 000100 Access the configuration bus for readback
JPROGRAM 001011 Equivalent to PROGRAM_B pin
JSTART 001100 Clocks the startup sequence
JSHUTDOWN 001101 Clocks the shutdown sequence
SYSMON_DRP 110111 System Monitor DRP access through JTAG. See the UltraScale Architecture System Monitor User Guide (UG580).
ISC_NOOP 010100 No operation
RESERVED All other codes AMD reserved instructions
  1. Instruction register is larger for devices based on SSI technology (see Table 2). See the BSDL files for device-specific information.

The following table shows the instruction capture values loaded into the IR as part of an instruction scan sequence.

Table 2. UltraScale FPGA Instruction Capture Values Loaded into IR as Part of an Instruction Scan Sequence
TDI IR[5] IR[4] IR[3] IR[2] IR[1:0] → TDO
DONE INIT ISC_ENABLED ISC_DONE 01
  1. INIT is the INIT_B_INTERNAL_SIGNAL_STATUS bit.
  2. Instruction register is larger for devices based on SSI technology (see Table 2). See the BSDL files for device-specific information.