IPROG Using ICAP - IPROG Using ICAP - UG570

UltraScale Architecture Configuration User Guide (UG570)
Document ID
UG570
Release Date
2025-03-04
Revision
1.20.1 English

The IPROG command can also be sent through ICAP using the ICAPE3 primitive. After a successful configuration, the user design determines the start address of the next bitstream, sets the WBSTAR register, and then issues an IPROG command using ICAP.

The command sequence is:

  1. Send the Sync word.
  2. Program the WBSTAR register for the next bitstream start address (see Warm Boot Start Address Register (10000)).
  3. Send the IPROG command.

The following table shows an example bitstream for the IPROG command using ICAP.

Table 1. Example Bitstream for IPROG through ICAP
Configuration Data (hex) 1 Explanation
FFFFFFFF Dummy word
AA995566 Sync word
20000000 Type 1 NOOP
30020001 Type 1 Write 1 words to WBSTAR
00000000 Warm boot start address (Load the desired address)
30008001 Type 1 Write 1 words to CMD
0000000F IPROG command
20000000 Type 1 NOOP
  1. See Parallel Bus Bit Order.

After the configuration logic receives the IPROG command, the FPGA resets everything except the dedicated reconfiguration logic, and the INIT_B and DONE pins go Low. After the FPGA clears all configuration memory, INIT_B goes High again. Then, the value in WBSTAR is used for the bitstream starting address. The configuration mode determines which pins are controlled by WBSTAR. See the following table.

Table 2. WBSTAR Controlled Pins According to Configuration Mode
Configuration Mode Pins Controlled by WBSTAR
Master SPI START_ADDR is sent to the flash device serially.
Master BPI RS[1:0], A[28:00]

RS[1:0] is controllable by WBSTAR in BPI mode only. The START_ADDR field is only meaningful for the BPI and SPI modes.

Figure 1. IPROG in BPI Modes

Notes relevant to the previous figure:

  1. All BPI pins, except the CCLK, FCS_B, and D[03:00] pins, are multi-function I/Os. After configuration is finished (the DONE pins goes High), these pins become user I/Os and can be controlled by user logic to access flash for user data storage and programming.
  2. In this example, RS[1:0] is set to 2'b11. During IPROG reconfiguration, the RS[1:0] pins override the external pull-up and pull-down resistors. You can specify any RS[1:0] value in the WBSTAR register using BITSTREAM.CONFIG.REVISIONSELECT.