WBSTAR and the
IPROG command can be embedded inside a bitstream. A safe bitstream is
stored at address 0 (in BPI or SPI mode). Later, a new application bitstream can be added to
flash by modifying the WBSTAR and the IPROG command in the
first bitstream. The FPGA directly loads the new bitstream. If the new bitstream fails,
configuration falls back to the original bitstream (see Fallback MultiBoot). The AMD tools insert the blank
write into WBSTAR and a place holder for the IPROG command
in every FPGA bitstream. For example, WBSTAR can be modified to a the
required start address (see Warm Boot Start Address Register (10000)). A
NULL command after WBSTAR can be modified to
IPROG by setting the four LSB bits to all ones (see Command Register (00100)).
The following figure illustrates this use model.