The ICAPE3 provides post-configuration access to the configuration functions of the FPGA from the FPGA logic. Using this component, commands and data can be written to and read from the configuration logic. The ICAPE3 interface is similar to that for the external slave SelectMAP parallel 32-bit interface, including bit swapping (see Parallel Bus Bit Order). However, the ICAPE3 has independent input and output buses; the CSIB input ignores the input bus but the output bus can continue to toggle.
Because you can send an unencrypted partial bitstream and can perform readback through the ICAPE3 interface, if you are concerned about security you should not connect the ICAPE3 component to external device pins. Because the improper use of this function can have a negative effect on the functionality and reliability of the FPGA, you should not use this element unless you are very familiar with its capabilities.
ICAPE3 can be useful in MultiBoot and active partial reconfiguration applications. ICAPE3 instantiation is required to issue an IPROG command that triggers the device to reload itself from the address specified in the WBSTAR (Warm Boot Starting Address) register. The WBSTAR register holds the address that the configuration controller uses after an IPROG command is issued.
Similar functionality is provided by the MCAP. Like ICAP, the MCAP can only be used after initial configuration, but it does not support readback. If Persist is set, the ICAPE3 is disabled. In addition, JTAG and MCAP have priority over ICAPE3.
The ICAPE3 for the UltraScale architecture-based FPGAs supports higher frequency and more output signals than were available in the ICAPE2 for the 7 series FPGAs. ICAPE3 only supports 32-bit interfaces, and does not have the ICAP_WIDTH attribute from the ICAPE2. ICAPE2 instantiations from 7 series designs are automatically migrated to ICAPE3 for the UltraScale FPGAs. The ICAPE3 is automatically used by some AMD IP, including the Soft Error Mitigation (SEM) IP.