Each FPGA should be used as if it had one ICAPE3
resource, although there are actually two ICAPE3 resources per die for improved SEU
protection. The tools automatically use the top ICAPE3 by default. Advanced users
can use the write_bitstream option BITSTREAM.Readback.ICAP_Select to select the
bottom resource. Control register 0 Bit 30 (ICAP_SELECT) enables the top ICAPE3 site
when set to 0 (default), and enables the bottom ICAPE3 site when
set to 1. User switching can be done by toggling CTL0<30>
using the currently active ICAPE3. The device can automatically switch between the
two ICAPE3 sites if enabled using the ICAP_AUTO_SWITCH attribute, using a sync word
on 8 LSBs.
For 3D ICs based on Stacked Silicon Interconnect (SSI) technology, the ICAPE3 of one Super Logic Region (SLR) is defined as the master, with the ability to read from and write to all other SLRs. The tools automatically place an instantiated ICAPE3 in the correct master SLR. When the mode pins are set to JTAG mode, the master SLR ICAP cannot access the slave SLRs. Because JTAG mode is always available, the mode pins do not need to be set to JTAG mode for configuration.