I/O Transition at the End of Startup - I/O Transition at the End of Startup - UG570

In all Kintex UltraScale FPGAs except for the KU095, which have the multi-function configuration pins on HR I/O banks, if the VCCO for the bank is 1.8V or lower, and if a pin on that bank is Low or floating, then the input might have a 0-1-0 transition to the interconnect logic during configuration startup. Because this transition occurs after GWE enables the internal logic, it might affect the internal state of the device after configuration. Note that this applies not only to the multi-function configuration bank 65, but also bank 70 in the KU085 and KU115. The transition occurs one CFGCLK after EOS (End Of Startup). To avoid this transition, set V_{CCO_65} (and V_{CCO_70}) to 2.5V or 3.3V, or drive the pin High externally (see the following table). Otherwise, logic should be designed to ignore these affected input signals until at least 200 ns after one CFGCLK following the rising edge of EOS. CFGCLK and EOS can be monitored using the STARTUPE3 primitive.