Ganged Serial Configuration - Ganged Serial Configuration - UG570

More than one device can be configured simultaneously from the same bitstream using a ganged serial configuration setup (see the following figure). In this arrangement, the serial configuration pins are tied together such that each device sees the same signal transitions. One device is typically set for master SPI mode (to drive CCLK) while the others are set for slave serial mode. For ganged serial configuration, all devices must be identical.

Configuration can also be driven by an external configuration controller as shown in the following figure, reading the bitstream from flash or other memory.

Notes relevant to the previous figure:

1. The DONE pin is by default an open-drain output. See Configuration Pin Definitions for DONE signal details.
2. The INIT_B pin is a bidirectional, open-drain pin. An external pull-up resistor is required.
3. All devices must be identical (same IDCODE) and must be configured with the same bitstream.
4. See Figure 1 for a more detailed view of the slave serial connections.

There are several important considerations for ganged serial configuration:

Start-up sequencing (GTS)

GTS should be released before DONE or during the same cycle as DONE to ensure all devices are operational when all DONE pins have been released.

Connect all DONE pins if using a master device

It is important to connect the DONE pins for all devices in ganged serial configuration if one FPGA is used as the master device. Failing to connect the DONE pins can cause configuration to fail for individual devices in this case. If all devices are set for slave serial mode, the DONE pins can be disconnected (if the external CCLK source continues toggling until all DONE pins go High).

For debugging purposes, it is often helpful to have a way of disconnecting individual DONE pins from the common DONE signal.

DONE pin rise time

After all DONE pins are released, the DONE pin should rise from logic 0 to logic 1 in one CCLK cycle. If additional time is required for the DONE signal to rise, the DonePipe option can be set for all devices in the serial daisy chain.

Configuration clock (CCLK) as clock signal for board layout

The CCLK signal is relatively slow, but the edge rates on the AMD UltraScale™ FPGA’s input buffers are very fast. Even minor signal integrity problems on the CCLK signal can cause the configuration to fail. (Typical failure mode: DONE Low and INIT_B High.) Therefore, design practices that focus on signal integrity, including signal integrity simulation with IBIS, are recommended.

Signal fanout

Designers must focus on good signal integrity when using ganged serial configuration. Signal integrity simulation is recommended.

Files for ganged serial configuration

Files for ganged serial configuration are identical to the files used to configure single devices. There are no special file considerations.