Ganged Asynchronous BPI Configuration - Ganged Asynchronous BPI Configuration - UG570

UltraScale Architecture Configuration User Guide (UG570)

Document ID
UG570
Release Date
2025-03-04
Revision
1.20.1 English

It is also possible to configure multiple devices simultaneously with the same configuration bitstream by using a ganged master BPI configuration, using asynchronous read mode. The ganged BPI configuration is similar to that shown in Figure 1, but with the data bus connected to multiple FPGAs. The DONE and INIT_B pins on all devices are connected together.