All frames have a fixed, identical length of 3,936 bits (123 32-bit words). See Differences Between UltraScale FPGA Families.
The frame address register (FAR) is divided into four fields: block type, row address, column address, and minor address (see the following table for UltraScale FPGAs and the subsequent table for UltraScale+ FPGAs). The address can be written directly or can be auto-incremented at the end of each frame. The typical bitstream starts at address 0 and auto-increments to the final count.
| Address Type | Bit Index | Description |
|---|---|---|
| Reserved | [31:26] | Reserved bits that are read as 0. |
| Block type | [25:23] |
Valid block types are CLB, I/O, CLK
( A normal bitstream does not include types
|
| Row address | [22:17] | Selects the current row. The row addresses increment from bottom to top. |
| Column address | [16:7] | Selects a major column, such as a column of CLBs. Column addresses start at 0 on the left and increase to the right. |
| Minor address | [6:0] | Selects a frame within a major column. |
| Address Type | Bit Index | Description |
|---|---|---|
| Block type | [26:24] |
Valid block types are CLB,
I/O, CLK ( A normal bitstream does not include types
|
| Row address | [23:18] | Selects the current row. The row addresses increment from bottom to top. |
| Column address | [17:8] | Selects a major column, such as a column of CLBs. Column addresses start at 0 on the left and increase to the right. |
| Minor address | [7:0] | Selects a frame within a major column. |