File Generation - File Generation - UG570

To implement a master BPI configuration mode solution you must create a design bitstream, then convert the bitstream into a flash programming file, and finally program the parallel NOR flash device. The following key properties should be reviewed when generating a bitstream for the master BPI configuration mode. These properties are also available through the Vivado tool Edit Device Properties dialog box. Refer to Vivado Design Suite User Guide: Programming and Debugging (UG908) for more details.

The external master configuration clock (EMCCLK) property (BITSTREAM.CONFIG.EXTMASTERCCLK_EN) can be used in master modes to get a more precise configuration clock. The bitstream property must be set to enable the EMCCLK and to set the desired divider option. See External Master Configuration Clock (EMCCLK) Option for additional details.

set_property BITSTREAM.CONFIG.EXTMASTERCCLK_EN Disable|Div-1|Div-2|Div-3|Div-4|Div-6|Div-8|Div-12|Div-16|Div-24|Div-48

For faster performance, synchronous reads can be enabled for select parallel NOR flash. Specify the property BITSTREAM.CONFIG.BPI_SYNC_MODE with Type1 option or Type2 option according to what the selected family supports.

set_property BITSTREAM.CONFIG.BPI_SYNC_MODE Disable|Type1|Type2

If master BPI configuration with asynchronous read is required, but a faster performance is desired, the page mode and read cycle options can be used. To enable these features use the properties BITSTREAM.CONFIG.BPI_PAGE_SIZE and BITSTREAM.CONFIG.BPI_1ST_READ_CYCLE:

set_property BITSTREAM.CONFIG.BPI_PAGE_SIZE 1|4|8

• Page sizes are 1 (default), 4, or 8. If the actual flash page size is larger than 8, the value of 8 should be used to maximize the efficiency.

set_property BITSTREAM.CONFIG.BPI_1ST_READ_CYCLE 1|2|3|4

• First access CCLK cycles of 1 (default), 2, 3, or 4. CCLK cycles must be 1 if the page size is 1.

After bitstream generation it is also important during flash programming file generation to ensure the data ordering is setup correctly. On AMD FPGAs, data bit D00 is the most-significant bit (MSB) and bit D15 is the least significant bit (LSB). Consequently, it is crucial to understand how the data ordering in the configuration data file corresponds to the data ordering expected by the FPGA. UltraScale FPGA bitstream files (.bit, .rbt) are never bit-swapped. By default, for the BPI and SelectMAP modes the .mcs file formats are bit-swapped (see Bit Swapping). This convention is consistent across all AMD FPGAs. The master BPI configuration mode data ordering is the same as the SelectMAP data ordering. During the flash programming file generation the data bus width option must be set to x8 or x16 appropriately based on the target parallel NOR flash. Refer to Vivado Design Suite User Guide: Programming and Debugging (UG908) for details.