The FPGA MultiBoot and fallback features support updating bitstream images dynamically in the field. The FPGA MultiBoot feature enables switching between images on the fly. When an error is detected during the MultiBoot configuration process, the FPGA can trigger a fallback feature that ensures a known good design can be loaded into the device. The MultiBoot and fallback feature can be used with all master configuration modes.
When fallback occurs, an internally generated pulse resets
the entire configuration logic, except for the dedicated MultiBoot logic,
the WBSTAR (warm boot start address), the BSPI, and the BOOTSTS (boot
status) registers. This reset pulse pulls INIT_B and
DONE Low, clears the configuration memory, and
restarts the configuration process from address 0 with the revision select
(RS) pins driven to 00 (in BPI mode). After the reset, the bitstream
overwrites the WBSTAR starting address.
During configuration, the following errors can trigger fallback:
- An IDCODE error
- A CRC error
- A Watchdog Timer timeout error
- A BPI address wraparound error
Fallback can also be enabled with the bitstream option
ConfigFallback (BITSTREAM.CONFIG.CONFIGFALLBACK ENABLE). Embedded IPROG is
ignored during fallback reconfiguration. The Watchdog Timer is disabled
during fallback reconfiguration. If fallback reconfiguration fails,
configuration stops and both INIT_B and
DONE are held Low.
Implementation of a robust in-system update solution involves a set of decisions. First, a method for system setup needs to be determined. Next, design considerations can be added for a specific configuration mode. Finally, HDL design considerations need to be taken into account and files need to be generated properly. This chapter walks through each stage of this process.