To use the Watchdog Timer to monitor the bitstream
configuration, set the bitstream property BITSTREAM.CONFIG.TIMER_CFG, or set TIMER_CFG_MON to
1 and the desired TIMER_VALUE in a write to the TIMER register in the
bitstream. The TIMER_VALUE should be adequate to cover the entire FPGA configuration time
until start-up is complete. Any wait time in start-up for DCI match,
MMCM lock, or DONE should also be included.
After it is enabled, the Watchdog Timer starts to count down. If the timer reaches 0 and the FPGA has not reached the final state of start-up, a watchdog timeout error occurs and triggers a fallback configuration.