External Master Configuration Clock (EMCCLK) Option - External Master Configuration Clock (EMCCLK) Option - UG570

By default, the master configuration modes use an internally generated configuration clock source CCLK. Using this clock option is convenient because an external clock generator source is not required. However, for applications where configuration time reduction is critical, the external master configuration clock (EMCCLK) should be used. The EMCCLK clock allows the use of a more precise external clock source than the FPGA's internal clock with the master CCLK frequency tolerance (F_MCCKTOL). For example, when the master CCLK has a maximum frequency of 150 MHz, a 35% tolerance means that the ConfigRate setting cannot be faster than 111 MHz. However, an external clock source can be applied as fast as the specification allows. UltraScale FPGAs support the ability to dynamically switch to an external clock source (EMCCLK) when in a master mode.

Enable the external clock source option by:

1. Enabling the EXTMASTERCCLK_EN bitstream generation option
2. Defining the EMCCLK target voltage (set the CONFIG_VOLTAGE property)
3. Connecting EMCCLK on the board to your board's oscillator or other clock source

set_property BITSTREAM.CONFIG.EXTMASTERCCLK_EN Disable|Div-1|Div-2 |Div-3|Div-4|Div-6|Div-8|Div-12|Div-16|Div-24|Div-48

The default is disable (use the internal CCLK).

Connect the EMCCLK input to the oscillator or other clock source on the board. Use good signal integrity design practices, especially for very high-speed clocks, to avoid signal integrity issues that can cause errors during configuration. EMCCLK is a single-ended clock input.

The configuration begins with the CCLK generated by the FPGA internal oscillator until the bitstream header is read. If the EMCCLK option is enabled then the FPGA switches from the internal oscillator to the clock found on the EMCCLK pin.