By default, the master BPI configuration
mode uses an internally generated configuration clock source CCLK. Using this
clock option is convenient because an external clock generator source is not required.
However, for applications where configuration time reduction is critical the external master
configuration clock (EMCCLK) should be used. The EMCCLK
clock allows the use of a more precise external clock source than the FPGA's internal clock
with the master CCLK frequency tolerance (FMCCKTOL). UltraScale FPGAs support the ability to dynamically switch to an
external clock source (EMCCLK) when in master BPI mode. For more details, see
External Master Configuration Clock (EMCCLK) Option.