EFUSE_USR - EFUSE_USR - UG570

UltraScale Architecture Configuration User Guide (UG570)

Document ID
UG570
Release Date
2025-03-04
Revision
1.20.1 English

Each AMD Kintex™ UltraScale™ and AMD Virtex™ UltraScale™ device has a one set of 32 nonvolatile, user-defined, one-time-programmable eFUSE bits. These bits are commonly programmed by the user to define a custom user design ID. Programming is done through the JTAG port. Programming can be done using the AMD configuration tools and cables, or on a third-party programmer.

These 32 bits define the values in the FUSE_USER configuration register. Depending on the read/write access bits in the CNTL register, the 32 bits can be programmed and read through the JTAG port, with bit 0 shifted out first.

For internal access, the EFUSE_USR primitive must be instantiated. EFUSE_USR provides asynchronous parallel access to all 32 bits.

The EFUSE_USR primitive is identical to that in the 7 series and will directly migrate.