3D ICs using SSI (Stacked Silicon Interconnect) technology support the same configuration modes as the monolithic devices. See the UltraScale Architecture and Product Data Sheet: Overview (DS890) and the 3D ICs website for more information on devices using SSI technology.
3D ICs have multiple super logic regions (SLRs), each with its own configuration controller. One SLR is defined as the master, while the others are the slaves (see the following table). The configuration banks and the PCIe blocks that support tandem configuration are always located in the master SLR. The SLRs are numbered from 0 at the bottom of the device floorplan.
| Device | Master SLR Index | Slave SLR Index |
|---|---|---|
| KU085 | SLR0 | SLR1 |
| KU115 | SLR0 | SLR1 |
| VU125 | SLR0 | SLR1 |
| VU160 | SLR1 | SLR0 and SLR2 |
| VU190 | SLR1 | SLR0 and SLR2 |
| VU440 | SLR1 | SLR0 and SLR2 |
| VU5P | SLR0 | SLR1 |
| VU7P | SLR0 | SLR1 |
| VU9P | SLR1 | SLR0 and SLR2 |
| VU11P | SLR0 | SLR1 and SLR2 |
| VU13P | SLR1 | SLR0, SLR2, and SLR3 |
| VU19P | SLR1 | SLR0, SLR2, and SLR3 |
| VU27P | SLR1 | SLR0, SLR2, and SLR3 |
| VU29P | SLR1 | SLR0, SLR2, and SLR3 |
| VU35P | SLR0 | SLR1 |
| VU37P | SLR0 | SLR1 and SLR2 |
| VU45P | SLR0 | SLR1 |
| VU47P | SLR0 | SLR1 and SLR2 |
| VU57P | SLR0 | SLR1 and SLR2 |
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