Differences from Previous Generations - Differences from Previous Generations - UG570

UltraScale architecture-based FPGAs support similar configuration interfaces as the 7 series FPGAs, with most improvements targeted at improving configuration performance. The following table summarizes the key differences in available configuration modes.

The master configuration modes are optimized to work with standard third-party flash memories. The SPI mode interfaces to standard x1, x2, or x4 serial NOR flash memories, while the BPI mode interfaces to x8 or x16 parallel NOR flash memories.

The UltraScale architecture-based FPGAs add a new configuration mode for configuring from two quad SPI flash memories in parallel. The resulting x8 configuration reduces the configuration time while still allowing for the use of standard, high-speed, low-cost serial NOR configuration memories.

This section describes other performance improvements.

• A higher performance internal configuration clock (CCLK) provides up to double the max frequency with less frequency variation.
• Because a significant amount of the power-up configuration time can be the power-on reset (POR) delay, the UltraScale architecture-based FPGAs offer a dedicated pin (POR_OVERRIDE) that can be set to reduce the delay when you know the power supplies will ramp quickly enough.
• The internal scanning for configuration bit errors caused by single event upsets (SEU) is also faster, reducing the time to mitigate an error.
• A new AES-GCM algorithm for decrypting encrypted bitstreams makes secure configuration performance on par with unencrypted configuration. The pin name for the RAM-based encryption key backup supply is V_BATT instead of V _CCBATT .
• The Device DNA unique identifier is increased from 57 bits to 96 bits.

The UltraScale architecture-based FPGAs combine RDWR_B and FCS_B on one pin and move it into the dedicated configuration bank 0. CSI_B and ADV_B are combined on another pin. The I/O flexibility is maximized by reducing the number of pins required for configuration.

Other configuration pins that were dual-purpose I/O in the 7 series and are dedicated in bank 0 for the UltraScale architecture-based FPGAs include the first four data pins D[03:00] and the control pin for pull-ups during configuration, PUDC_B.

The UltraScale architecture-based FPGAs use only one I/O bank (bank 65) for multi-function pins needed for some configuration modes. The pin-outs describe the banks for each pin. Configuration interfaces can be powered at 1.5V, 1.8V, 2.5V, or 3.3V. See Configuration Banks Voltage Select (Kintex UltraScale and Virtex UltraScale FPGAs) for voltage ranges supported by mode and by device.

The UltraScale architecture-based FPGAs continue to support the Internal Configuration Access Port (ICAP), providing direct access between FPGA logic and configuration functions. The ICAP interface is similar to the SelectMAP interface, and allows user logic to initiate active reconfiguration. A new Media Configuration Access Port (MCAP) provides a similar connection to the integrated block for PCI Express. A small initial bitstream can be loaded quickly at power-up to enable the PCIe interface, and then the rest of the configuration can be loaded through the PCIe interface - this is known as Tandem PCIe. Alternatively, the second part of the configuration can be loaded through the standard configuration interfaces - this is known as Tandem PROM. See the UltraScale Devices Gen3 Integrated Block for PCI Express LogiCORE IP Product Guide (PG156) or the UltraScale+ Devices Integrated Block for PCI Express LogiCORE IP Product Guide (PG213) for information on tandem configuration solutions.

Design Entry provides details on the configuration and boundary scan components. The following primitives are different than the 7 series primitives:

• DNA_PORTE2
  • Extended to 96 bits
• FRAME_ECCE3
  • Used by Soft Error Mitigation (SEM) IP
• FRAME_ECCE4
  • Used by Soft Error Mitigation (SEM) IP
• STARTUPE3
  • Adds access to more configuration pins (FCS_B and D[03:00])
• MASTER_JTAG
  • New feature to provide internal, secure access to the JTAG logic
• CAPTUREE2
  • No longer supported
  • Use the AMD Vivado™ Integrated Logic Analyzer to monitor the internal signals of a design. See the Integrated Logic Analyzer LogiCORE IP Product Guide (PG172).
• ICAPE3
  • Adds additional status signals
  • Supports x32 only