Differences Between UltraScale FPGA Families - Differences Between UltraScale FPGA Families - UG570

UltraScale Architecture Configuration User Guide (UG570)

Document ID
UG570
Release Date
2025-03-04
Revision
1.20.1 English

This document uses the Kintex UltraScale and Virtex UltraScale families as the basis for descriptions and examples. The following defines some of the differences in the Artix UltraScale+, Kintex UltraScale+, and Virtex UltraScale+ families:

  • Master serial and master SelectMAP configuration modes are not supported in the UltraScale+ FPGAs. These modes are not recommended in the other UltraScale families.
  • The configuration interface can operate only at 1.8V or 1.5V in the UltraScale+ FPGAs. There is no CFGBVS pin in UltraScale+ devices. When migrating from an UltraScale FPGA to an UltraScale+ FPGA, the CFGBVS pin location becomes RSVDGND and must be connected to GND.
  • The configuration timing and configuration rate options are different between UltraScale FPGAs and UltraScale+ FPGAs. The configuration frame size is 123 32-bit words in UltraScale FPGAs and 93 32-bit words in UltraScale+ FPGAs.