Device Resources and Configuration Bitstream Lengths - Device Resources and Configuration Bitstream Lengths

Device Resources and Configuration Bitstream Lengths - Device Resources and Configuration Bitstream Lengths - UG570

UltraScale Architecture Configuration User Guide (UG570)

Document ID

UG570

Release Date

2025-03-04

Revision

1.20.1 English

A complete bitstream for each device has a fixed length for a given set of configuration options, independent of the logic used. However, bitstream options such as compression (BITSTREAM.GENERAL.COMPRESS) can change the required bitstream length. Because compressed bitstreams can change in size between design iterations, memory space should be reserved for the full uncompressed bitstream. The following table shows the default bitstream lengths and the subsequent table shows other device-specific information.

Table 1. Bitstream Length for UltraScale Architecture-based FPGAs
Device	Configuration Bitstream Length (bits)	Minimum Configuration Flash Memory Size (Mb)	Configuration Frames	Frame Length in Words¹	Configuration Array Size in Words²	Configuration Overhead in Words
Kintex UltraScale FPGAs
KU025	128,055,264	128	32,530	123	4,001,190	537
KU035	128,055,264	128	32,530	123	4,001,190	537
KU040	128,055,264	128	32,530	123	4,001,190	537
KU060	192,999,264	256	49,030	123	6,030,690	537
KU085	386,012,160	512	98,060	123	12,061,380	1,500
KU095	286,746,912	512	72,848	123	8,960,304	537
KU115	386,012,160	512	98,060	123	12,061,380	1,500
Virtex UltraScale FPGAs
VU065	200,713,824	256	50,990	123	6,271,770	537
VU080	286,746,912	512	72,848	123	8,960,304	537
VU095	286,746,912	512	72,848	123	8,960,304	537
VU125	401,441,280	512	101,980	123	12,543,540	1,500
VU160	602,155,936	1,024	152,970	123	18,815,310	2,063
VU190	602,155,936	1,024	152,970	123	18,815,310	2,063
VU440	1,031,730,976	1,024	262,110	123	32,239,530	2,063
Artix UltraScale+ FPGAs
AU7P	24,586,336	32	8,256	93	767,808	515
AU10P	42,799,456	64	14,376	93	1,336,968	515
AU15P	42,799,456	64	14,376	93	1,336,968	515
AU20P	123,449,056	128	41,476	93	3,857,268	515
AU25P	123,449,056	128	41,476	93	3,857,268	515
Kintex UltraScale+ FPGAs
KU3P	123,449,056	128	41,476	93	3,857,268	515
KU5P	123,449,056	128	41,476	93	3,857,268	515
KU9P	212,086,240	256	71,260	93	6,627,180	515
KU11P	188,647,264	256	63,384	93	5,894,712	515
KU13P	229,605,952	256	77,147	93	7,174,671	515
KU15P	290,744,896	512	97,691	93	9,085,263	515
KU19P	521,959,264	512	175,384	93	16,310,712	515
Virtex UltraScale+ FPGAs
VU3P	213,752,800	256	71,820	93	6,679,260	515
VU5P	427,519,232	512	143,640	93	13,358,520	1,456
VU7P	427,519,232	512	143,640	93	13,358,520	1,456
VU9P	641,272,864	1,024	215,460	93	20,037,780	1,997
VU11P	679,913,248	1,024	228,444	93	21,245,292	1,997
VU13P	906,547,008	1,024	304,592	93	28,327,056	2,538
VU19P	1,592,895,936	2,048	535,220	93	49,775,460	2,538
VU23P	521,959,264	512	175,384	93	16,310,712	515
VU27P	906,547,008	1,024	304,592	93	28,327,056	2,538
VU29P	906,547,008	1,024	304,592	93	28,327,056	2,538
VU31P	226,632,928	256	76,148	93	7,081,764	515
VU33P	226,632,928	256	76,148	93	7,081,764	515
VU35P	453,279,488	512	152,296	93	14,163,528	1456
VU37P	679,913,248	1024	228,444	93	21,245,292	1997
VU45P	453,279,488	512	152,296	93	14,163,528	1456
VU47P	679,913,248	1,024	228,444	93	21,245,292	1997
VU57P	679,913,248	1,024	228,444	93	21,245,292	1997
All UltraScale FPGA configuration frames consist of 123 32-bit words. All UltraScale+ FPGA configuration frames consist of 93 32-bit words. Configuration array size equals the number of configuration frames times the number of words per frame.

Table 2. JTAG and IDCODE for UltraScale Architecture-based FPGAs
Device	JTAG/Device IDCODE[31:0] (hex) ¹ ²	Production IDCODE Revision	JTAG Instruction Length (bits)
Kintex UltraScale FPGAs
KU025	X3824093	1 or later	6
KU035	X3823093	1 or later	6
KU040	X3822093	1 or later	6
KU060	X3919093	1 or later	6
KU085	X380F093	1 or later	12
KU095	X3844093	2 or later	6
KU115	X390D093	1 or later	12
Virtex UltraScale FPGAs
VU065	X3939093	0 or later	6
VU080	X3843093	2 or later	6
VU095	X3842093	2 or later	6
VU125	X392D093	1 or later	12
VU160	X3933093	1 or later	18
VU190	X3931093	1 or later	18
VU440	X396D093	1 or later	18
Artix UltraScale+ FPGAs
AU7P	X4AF6093	0 or later	6
AU10P	X4AC4093	0 or later	6
AU15P	X4AC2093	0 or later	6
AU20P	X4A65093	0 or later	6
AU25P	X4A64093	0 or later	6
Kintex UltraScale+ FPGAs
KU3P	X4A63093	0 or later	6
KU5P	X4A62093	0 or later	6
KU9P	X484A093	2 or later	6
KU11P	X4A4E093	0 or later	6
KU13P	X4A52093	1 or later	6
KU15P	X4A56093	1 or later	6
KU19P	X4ACF093	0 or later	6
Virtex UltraScale+ FPGAs
VU3P	X4B39093	1 or later	6
VU5P	X4B2B093	1 or later	12
VU7P	X4B29093	1 or later	12
VU9P	X4B31093	1 or later	18
VU11P	X4B49093	0 or later	18
VU13P	X4B51093	0 or later	24
VU19P	X4BA1093	0 or later	24
VU23P	X4ACE093	0 or later	6
VU27P	X4B43093	0 or later	24
VU29P	X4B41093	0 or later	24
VU31P	X4B6B093	1 or later	6
VU33P	X4B69093	1 or later	6
VU35P	X4B71093	1 or later	12
VU37P	X4B79093	1 or later	18
VU45P	X4B73093	1 or later	12
VU47P	X4B7B093	1 or later	18
VU57P	X4B61093	0 or later	18
The “X” in the JTAG IDCODE value represents the revision field (IDCODE[31:28]) which can vary. If the IDCODE does not match the expected value, ensure that PROGRAM_B is not held Low.