Device Power-Up (Step 1) - Device Power-Up (Step 1)

Device Power-Up (Step 1) - Device Power-Up (Step 1) - UG570

UltraScale Architecture Configuration User Guide (UG570)

Document ID

UG570

Release Date

2025-03-04

Revision

1.20.1 English

Figure 1. Device Power-Up (Step 1)

For configuration, devices require power on the V_{CCO_0} , V_CCAUX, V_{CCAUX_IO}, V_CCBRAM, V_CCINT, and V_{CCINT_IO} pins. Power sequencing requirements are described in the respective data sheet ( Kintex UltraScale FPGAs Data Sheet: DC and AC Switching Characteristics (DS892) or Virtex UltraScale FPGAs Data Sheet: DC and AC Switching Characteristics (DS893)).

All JTAG and serial configuration pins are located in a separate, dedicated bank with a dedicated voltage supply (V_{CCO_0}). None of the I/O voltage supplies except V_{CCO_0} needs to be powered for FPGA configuration in JTAG or serial modes (up to SPI x4) when RS[1:0] is not used. All dedicated input pins operate at the V_{CCO_0} LVCMOS level. All active dedicated output pins operate at the V_{CCO_0} voltage level with the output standard set to LVCMOS, 12 mA drive, fast slew rate.

The multi-function pins are located in bank 65. For all modes that use multi-function I/O (for example, master BPI, SPI x8, SelectMAP), the associated V_{CCO_65} must be connected to the appropriate voltage to match the I/O standard of the configuration device. The pins are also LVCMOS, 12 mA drive, fast slew rate during configuration. If the Persist option is used (see Persist Option), the multi-function I/O for the selected configuration mode remain active after configuration, with the I/O standard set to the default of LVCMOS, 12 mA drive, fast slew rate.

The following table shows the power supplies required for configuration. Power-Up Timing shows the timing for power-up. Refer to the data sheet for voltage ratings. Standard I/O voltage levels supported for configuration are 1.5V, 1.8V, 2.5V, and 3.3V. None of the I/O voltage supplies except V_{CCO_0} needs to be powered for configuration in JTAG mode. When configuration modes are selected that use the multi-function pins (that is, serial, master BPI, SPI, SelectMAP), VCCO_65 must also be supplied. In Virtex UltraScale devices, and in the Kintex UltraScale KU095, bank 65 is an HP I/O bank, and therefore configuration interfaces requiring bank 65 must operate at 1.5V or 1.8V.

Power Supplies Required for Configuration

Pin Name	Description
V_CCINT	Internal supply voltage.
V_{CCINT_IO}	Internal supply voltage for the I/O banks.
V_BATT ¹	AES decryptor key memory backup power supply; If the key memory is not used, you should tie this pin to V_CCAUX or GND.
V_CCAUX	Auxiliary supply voltage.
V_{CCAUX_IO_#}	Auxiliary supply voltage for the I/O banks.
V_CCBRAM	Supply voltage for the block RAM.
V_{CCO_0}	Configuration bank supply voltage.
V_{CCO_65}	Multi-function configuration bank supply voltage.
VBATT is required only when an AES key is stored in the FPGA battery-backed RAM for decryption of an encrypted bitstream.

Power-Up Timing

Symbol	Description
T_PL	Program latency.
T_POR	Power-on reset (POR).
T_ICCK	CCLK output delay.
T_PROGRAM	Program pulse width.
See the data sheet for power-up timing characteristics.

The following figure shows the power-up waveforms.

Figure 2. Device Power-Up Timing

To ensure proper power-on behavior, the guidelines in the respective UltraScale family data sheet must be followed. Power supplies must rise monotonically within the specified ramp rate. If this is not possible, delay configuration by holding the INIT_B or PROGRAM_B Low (see Delaying Configuration) while the system power reaches the minimum recommended operating voltages. The T_POR specification begins when the last of the monitored supplies (V_CCINT, V_CCAUX, V_CCBRAM, V_{CCO_0}) reaches 95% of its recommended operating condition voltage. The actual tPOR delay begins earlier depending on the thresholds of the monitored voltages, resulting in a smaller minimum specification with a slower ramp. Note that the recommended power-on sequence in the data sheet, to achieve minimum current draw and ensure that the I/Os are 3-stated at power-on, has V_CCO applied last. The T_POR time includes a built-in delay to allow for voltages to stabilize before beginning configuration. For applications where power-on time is important, the POR_OVERRIDE pin can be tied to V_CCINT, which shortens the built-in delay. See the data sheet for the resulting T_POR time when the supplies are ramped quickly and POR_OVERRIDE is tied to V_CCINT. Note that V_CCINT is recommended to ramp first. For the standard T_POR delay, tie POR_OVERRIDE to ground. See Power-On Reset.

UltraScale devices with multiple SLRs (this does not apply to UltraScale+ devices) can have the weak pull-up temporarily enabled on I/Os in the Slave SLR during the configuration sequence (between power on and assertion of the INIT_B configuration signal). In some boards, this can cause an undesired 0-1-0 transition on I/O in the slave SLR. It is recommended that any I/O pins in the slave SLR sensitive to a 0-1-0 transition during configuration be connected to I/Os in the Master SLR or include external pull-downs of 1 kΩ or stronger to the pin.

Delaying Configuration

To delay configuration, the INIT_B or PROGRAM_B pin should be held Low during initialization (see the previous figure). When INIT_B has gone High, configuration cannot be delayed subsequently by pulling INIT_B Low.

The signals relating to initialization and delaying configuration are defined in the following table.

Table 1. Signals Relating to Initialization and Delaying Configuration
Signal Name	Type	Access¹	Description
INIT_B	Input, output, or open drain	Externally accessible through the INIT_B pin	From power-on reset or PROGRAM_B reset, INIT_B is driven Low, indicating that the FPGA is initializing (clearing) its configuration memory. Before the Mode pins are sampled, INIT_B is an input that can be held Low to delay configuration. After the Mode pins are sampled, INIT_B is an open-drain, active-Low output that indicates if a CRC error occurred during configuration or a readback CRC error occurred after configuration (when enabled): `0`: CRC or IDCODE error (DONE is Low) or Readback CRC error (DONE is High and Readback CRC is enabled). `1`: No CRC error, initialization is complete.
INIT_B_INTERNAL_ SIGNAL_STATUS	Status	Internal signal, accessible through the FPGA status register	Indicates whether INIT_B signal is internally released.
MODE_STATUS[2:0]	Status	Internal signals, accessible through the FPGA status register	Reflects the values sampled on the mode pins when the status is read.
PROGRAM_B	Input	Externally accessible through the PROGRAM_B pin.	Before the Mode pins are sampled, PROGRAM_B is an input that can be held Low to delay configuration.
Information on the FPGA status register is available in Table 1. Information on accessing the device status register through SelectMAP is available in Readback Verification and CRC. The status type is an internal status signal without a corresponding pin.

After power-up, the device can be re-configured by toggling the PROGRAM_B pin Low (see the following figure).

Figure 3. Re-configuring the Device by Toggling the PROGRAM_B Pin Low