In master SPI mode, the FPGA delivers the configuration clock. The FPGA master configuration clock frequency is set through the Vivado tool Edit Device Properties dialog box. The configuration rate option sets the nominal configuration clock frequency.
The configuration rate setting can be increased for a faster configuration time, if the timing requirements discussed in this section are satisfied. When determining a valid configuration rate setting, these timing parameters must be considered:
- FPGA nominal master
CCLKfrequency (configuration rate setting) - FPGA master
CCLKfrequency tolerance (FMCCKTOL) - SPI clock low to output valid (TSPITCO)
- FPGA data setup time (TSPIDCC)
To maximize performance, the FPGA needs to use the falling edge clocking mode to take advantage of the entire clock period (see SPI Configuration Timing). The following details assume this option has been enabled in the Vivado tool Edit Device Properties dialog box.
The FPGA master configuration clock has a
tolerance of FMCCKTOL. Due to the master configuration clock
tolerance (FMCCKTOL), the Vivado
tool Edit Device Properties dialog
box configuration rate option must be checked so that the period for the worst-case (fastest)
master CCLK frequency is greater than the sum of the FPGA address valid time,
SPI clock low to output valid, and FPGA setup time, as shown in the following equation.
The frequency tolerance of the FPGA master
configuration clock can be a significant factor in this calculation at higher CCLK rates. If
maximum configuration speeds are needed, it is recommended to use an external clock to
minimize the impact of that variable. This requires connection to the EMCCLK
pin and enabling this option in the Vivado tool
Edit Device Properties dialog
box.
Refer to the flash device data sheet to ensure that the flash selected limits (clock low/high time) satisfy the timing specifications and do not affect the CONFIGRATE setting.